ic

MWCT2016SHVPAR

Symbol
GPIO[144]/FCCU_ERR1/LPUART3_TX/LPSPI2_SIN/eMIOS_0_CH[23]_X/LPUART1_RTS/FXIO_D3/TRGMUX_OUT7/FCCU_ERR_IN1/EIRQ[15]/ADC0_P4/WKPU[19]1GPIO[143]/FCCU_ERR0/LPSPI2_SCK/eMIOS_0_CH[22]_X/CMP1_RRT/FXIO_D2/TRGMUX_OUT6/FCCU_ERR_IN0/LPUART1_CTS/LPUART3_RX/EIRQ[14]/ADC0_P32GPIO[97]/LPUART5_TX/eMIOS_0_CH[3]_G/LPSPI3_SCK/eMIOS_0_CH[17]_Y/FXIO_D1/TRGMUX_OUT2/EIRQ[9]/ADC0_P03GPIO[96]/eMIOS_0_CH[2]_G/LPSPI3_SOUT/eMIOS_0_CH[16]_X/FXIO_D0/TRGMUX_OUT1/LPUART5_RX/EIRQ[8]/WKPU[6]/ADC0_P14GPIO[139]/LPUART4_TX/LPSPI2_PCS0/eMIOS_0_CH[1]_G/eMIOS_0_CH[21]_Y/FXIO_D5/TRGMUX_OUT5/EIRQ[10]/WKPU[28]/ADC0_P65GPIO[138]/LPSPI3_SIN/LPSPI2_PCS1/eMIOS_0_CH[20]_Y/CLKOUT_STANDBY/FXIO_D4/TRGMUX_OUT4/LPUART4_RX/EIRQ[9]/ADC0_P56GPIO[141]/eMIOS_1_CH[5]_H/LPSPI2_PCS2/LPSPI2_PCS0/FXIO_D5/EIRQ[12]/ADC1_S197VREFH8VREFL9VDD_HV_A10V2511VSS12V1113VSS14EXTAL15VSS16XTAL17GPIO[131]/CAN4_TX/eMIOS_0_CH[19]_Y/FXIO_D6/LPUART2_RTS/CMP0_OUT/LPUART5_RX/EIRQ[3]/TRGMUX_IN618GPIO[140]/CMP0_RRT/CAN5_TX/LPUART2_TX/eMIOS_1_CH[5]_H/FXIO_D8/FXIO_D7/EIRQ[11]19GPIO[113]/eMIOS_0_CH[18]_Y/LPSPI3_PCS0/FXIO_D9/CAN5_RX/LPUART2_RX/EIRQ[24]20GPIO[112]/eMIOS_0_CH[1]_G/LPSPI0_SIN/eMIOS_1_CH[15]_H/LPUART2_RTS/CMP0_IN521GPIO[111]/FXIO_D6/eMIOS_0_CH[0]_X/eMIOS_1_CH[14]_H/LPSPI0_SCK/FXIO_D10/CAN3_RX/LPUART2_CTS/EIRQ[31]/CMP0_IN122GPIO[137]/eMIOS_0_CH[7]_G/eMIOS_1_CH[13]_H/CAN3_TX/FXIO_D11/LPUART2_CTS/EIRQ[8]/CMP0_IN023GPIO[110]/eMIOS_0_CH[21]_Y/LPUART1_TX/LPI2C0_SCL/CMP0_RRT/CLKOUT_RUN/EIRQ[30]24GPIO[109]/eMIOS_0_CH[20]_Y/FXIO_D7/LPI2C0_SDA/LPUART1_RX/EIRQ[29]/WKPU[24]25GPIO[136]/LPSPI3_PCS1/eMIOS_0_CH[6]_G/FXIO_D12/FXIO_D8/EIRQ[7]/CMP0_IN326GPIO[37]/eMIOS_0_CH[5]_G/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT_RUN/eMIOS_1_CH[11]_H/EIRQ[13]/TRGMUX_IN027GPIO[36]/eMIOS_0_CH[4]_G/LPSPI0_SOUT/eMIOS_1_CH[10]_H/EIRQ[12]/TRGMUX_IN128GPIO[67]/eMIOS_0_CH[3]_G/CAN0_TX/LPUART0_TX/I3C0_PUR/EIRQ[3]/CMP0_IN429GPIO[66]/eMIOS_0_CH[2]_G/LPSPI3_PCS2/LPSPI0_PCS2/CAN0_RX/LPUART0_RX/EIRQ[2]/CMP0_IN230GPIO[103]/LPUART2_TX/LPSPI3_PCS3/LPSPI0_PCS3/EIRQ[15]/CMP0_IN631GPIO[102]/FXIO_D3/eMIOS_1_CH[12]_H/FXIO_D13/LPSPI0_PCS0/LPUART2_RX/EIRQ[14]/CMP0_IN732GPIO[101]/eMIOS_0_CH[19]_Y/eMIOS_0_CH[2]_G/I3C0_SDA/FXIO_D15/LPSPI0_PCS1/EIRQ[13]/TRGMUX_IN733GPIO[108]/eMIOS_0_CH[18]_Y/LPUART2_RTS/LPSPI0_SOUT/LPI2C1_HREQ/EIRQ[28]34GPIO[107]/eMIOS_0_CH[17]_Y/LPSPI0_SCK/LPUART2_CTS/EIRQ[27]35GPIO[106]/eMIOS_0_CH[16]_X/eMIOS_1_CH[10]_H/LPSPI0_SIN/CLKOUT_RUN/EIRQ[26]36VDD_HV_A37VSS38GPIO[65]/eMIOS_0_CH[1]_G/FXIO_D5/eMIOS_0_CH[15]_H/CAN3_RX/EIRQ[1]39GPIO[64]/CAN3_TX/eMIOS_0_CH[0]_X/eMIOS_0_CH[14]_H/EIRQ[0]40GPIO[105]/LPI2C1_SCL/FXIO_D0/LPUART6_TX/I3C0_SCL/eMIOS_0_CH[13]_H/FXIO_D10/EIRQ[25]41GPIO[104]/LPSPI3_SOUT/LPI2C1_SDA/I3C0_SDA/FXIO_D1/eMIOS_0_CH[12]_H/FXIO_D11/LPUART6_RX/EIRQ[24]42GPIO[81]/LPSPI3_SCK/I3C0_PUR/CAN2_TX/LPI2C1_SCLS/FXIO_D14/FXIO_D243GPIO[80]/LPSPI3_SIN/eMIOS_1_CH[9]_H/LPI2C1_SDAS/I3C0_SCL/FXIO_D15/LPI2C1_SDA/CAN2_RX/LPUART2_RX44GPIO[79]/CAN2_TX/eMIOS_0_CH[11]_H/LPSPI2_SCK/ADC0_MA[2]/LPUART2_TX/LCU1_OUT0/LPI2C1_SCL/EIRQ[23]/TRGMUX_IN845GPIO[78]/eMIOS_0_CH[10]_H/LPSPI2_PCS0/ADC0_MA[1]/eMIOS_1_CH[4]_H/LCU1_OUT1/FXIO_D16/CAN2_RX/EIRQ[22]/TRGMUX_IN946GPIO[35]/eMIOS_0_CH[9]_H/LPSPI2_SOUT/ADC0_MA[0]/CAN4_TX/LCU1_OUT2/FXIO_D17/EIRQ[11]/TRGMUX_IN247GPIO[34]/ADC1_MA[0]/eMIOS_0_CH[8]_X/LPSPI2_SIN/LCU1_OUT3/FXIO_D18/CAN4_RX/EIRQ[10]/TRGMUX_IN3/WKPU[8]48GPIO[77]/eMIOS_1_CH[3]_H/eMIOS_0_CH[23]_X/ADC1_MA[1]/FXIO_D16/LCU1_OUT8/EIRQ[21]49GPIO[76]/ADC1_MA[2]/eMIOS_1_CH[2]_H/eMIOS_0_CH[22]_X/LPSPI2_PCS1/FXIO_D19/LCU1_OUT9/EIRQ[20]50GPIO[8]/eMIOS_1_CH[12]_H/LPSPI2_SOUT/FXIO_D6/LPUART2_RX/EIRQ[16]/WKPU[23]/ADC0_P2100GPIO[9]/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/LPSPI3_PCS0/EIRQ[17]/WKPU[21]/ADC0_P799GPIO[4]/FXIO_D6/CMP0_OUT/JTAG_TMS/SWD_DIO/EIRQ[4]/ADC1_S1598GPIO[5]/RESET_b/EIRQ[5]97GPIO[68]/eMIOS_0_CH[8]_X/FXIO_D5/JTAG_TCK/SWD_CLK/EIRQ[4]/CMP1_IN396GPIO[69]/eMIOS_0_CH[16]_X/FXIO_D4/JTAG_TDI/LPI2C1_HREQ/EIRQ[5]/ADC1_S1495GPIO[128]/LPSPI0_SIN/FXIO_D3/LPUART7_RX/EIRQ[0]/WKPU[26]/ADC1_P294GPIO[129]/LPSPI0_SCK/FXIO_D2/LPUART7_TX/EIRQ[1]/ADC1_P393GPIO[10]/eMIOS_0_CH[12]_H/FXIO_D0/JTAG_TDO/TRACEnoETM_SWO/EIRQ[18]92GPIO[11]/CAN1_TX/eMIOS_0_CH[13]_H/eMIOS_1_CH[1]_H/FXIO_D1/CMP0_RRT/LPSPI1_PCS0/EIRQ[19]/ADC1_S1091GPIO[12]/LPSPI1_PCS5/eMIOS_0_CH[14]_H/CLKOUT_STANDBY/FXIO_D9/eMIOS_1_CH[2]_H/CMP1_OUT/CAN1_RX/EIRQ[20]/ADC1_P090GPIO[13]/LPSPI1_PCS4/eMIOS_0_CH[15]_H/FXIO_D8/eMIOS_1_CH[3]_H/EIRQ[21]/WKPU[4]/ADC1_P189GPIO[14]/eMIOS_1_CH[4]_H/LPSPI1_PCS3/FXIO_D14/EIRQ[22]/ADC1_P488VDD_HV_A87VSS86GPIO[130]/LPSPI0_SOUT/eMIOS_0_CH[3]_G/eMIOS_1_CH[8]_X/FXIO_D13/ADC0_MA[0]/LPUART1_CTS/EIRQ[2]/WKPU[27]/ADC1_P585GPIO[134]/LPSPI0_PCS2/LPUART1_RTS/eMIOS_1_CH[14]_H/FXIO_D12/ADC0_MA[1]/EIRQ[6]/ADC1_P6/WKPU[29]84GPIO[15]/eMIOS_0_CH[10]_H/LPSPI0_PCS3/LPSPI2_PCS3/FXIO_D31/LPUART6_RX/EIRQ[23]/ADC1_P7/WKPU[20]83GPIO[16]/eMIOS_0_CH[11]_H/LPSPI1_PCS2/LPSPI0_PCS4/LPUART6_TX/FXIO_D30/EIRQ[4]/ADC1_S13/WKPU[31]82GPIO[70]/LPI2C1_SDA/FXIO_D11/LPSPI1_PCS1/LCU0_OUT7/eMIOS_1_CH[6]_H/LPSPI0_PCS1/ADC0_MA[2]/CAN2_RX/LPUART1_RX/EIRQ[6]/WKPU[3]/ADC1_S1881GPIO[71]/FXIO_D10/LPUART1_TX/LPI2C1_SCL/LCU0_OUT6/eMIOS_1_CH[7]_H/LPSPI0_PCS0/CAN2_TX/LPI2C0_HREQ/EIRQ[7]/WKPU[2]/ADC1_S1680GPIO[0]/eMIOS_0_CH[17]_Y/LCU0_OUT4/FXIO_D2/eMIOS_1_CH[0]_X/LPSPI0_PCS7/TRGMUX_OUT3/LPUART0_CTS/EIRQ[0]/ADC0_S8/CMP1_IN079GPIO[1]/eMIOS_0_CH[9]_H/LPUART0_RTS/FXIO_D3/LCU0_OUT5/LPSPI0_PCS6/TRGMUX_OUT0/EIRQ[1]/ADC0_S9/CMP1_IN1/WKPU[5]78GPIO[40]/eMIOS_1_CH[15]_H/LCU0_OUT11/LPSPI0_PCS5/FXIO_D29/EIRQ[14]/ADC0_X[0]/WKPU[25]77GPIO[41]/eMIOS_1_CH[16]_X/LCU0_OUT10/FXIO_D28/EIRQ[15]/ADC0_X[1]/WKPU[17]76GPIO[42]/eMIOS_1_CH[17]_Y/LCU0_OUT9/FXIO_D27/EIRQ[24]/ADC0_X[2]75GPIO[43]/eMIOS_1_CH[18]_Y/LCU0_OUT8/FXIO_D26/LPI2C0_HREQ/EIRQ[25]/ADC0_X[3]/WKPU[16]74GPIO[2]/FCCU_ERR0/eMIOS_1_CH[19]_Y/FXIO_D4/LCU0_OUT3/FCCU_ERR_IN0/LPSPI1_SIN/LPUART0_RX/EIRQ[2]/ADC1_X[0]/WKPU[0]/CMP1_IN273GPIO[3]/FCCU_ERR1/eMIOS_1_CH[20]_Y/LPSPI1_SCK/LCU0_OUT2/FXIO_D5/LPUART0_TX/FCCU_ERR_IN1/EIRQ[3]/ADC1_S1772GPIO[98]/LCU0_OUT1/eMIOS_1_CH[21]_Y/LPSPI1_SOUT/FXIO_D4/FXIO_D6/LPUART3_TX/EIRQ[10]/TRGMUX_IN5/WKPU[9]/ADC0_S1671GPIO[99]/eMIOS_1_CH[22]_X/LPSPI1_PCS0/FXIO_D5/FXIO_D7/LCU0_OUT0/LPUART3_RX/EIRQ[11]/TRGMUX_IN4/NMI_b/WKPU[1]/ADC0_S1070GPIO[100]/eMIOS_1_CH[23]_X/LPSPI1_PCS1/LCU0_OUT6/EIRQ[12]/ADC0_S19/WKPU[22]69GPIO[44]/LPSPI3_PCS3/eMIOS_0_CH[0]_X/LCU0_OUT2/FXIO_D25/EIRQ[26]/ADC1_X[1]/WKPU[12]68GPIO[45]/LPSPI3_PCS2/eMIOS_0_CH[1]_G/FXIO_D8/LCU0_OUT3/FXIO_D24/EIRQ[27]/ADC0_S8/ADC1_S8/WKPU[11]67GPIO[46]/eMIOS_0_CH[2]_G/LPSPI1_SCK/LCU0_OUT7/FXIO_D23/LPUART7_RX/EIRQ[28]/ADC0_S9/ADC1_S966GPIO[47]/eMIOS_0_CH[3]_G/LPSPI1_SIN/LPUART7_TX/FXIO_D22/EIRQ[29]/ADC1_S11/WKPU[33]65GPIO[48]/eMIOS_0_CH[4]_G/LPSPI1_SOUT/LPUART4_TX/FXIO_D21/EIRQ[30]/WKPU[13]/ADC1_S1264GPIO[49]/eMIOS_0_CH[5]_G/LPSPI1_PCS3/eMIOS_1_CH[7]_H/LPSPI3_PCS0/FXIO_D20/LPUART4_RX/EIRQ[31]/ADC1_X[2]/WKPU[14]63VDD_HV_A62VSS61V1160GPIO[135]/eMIOS_0_CH[7]_G/LPSPI3_SCK/FXIO_D11/LPUART4_RX59GPIO[6]/LPSPI1_PCS1/eMIOS_1_CH[13]_H/FXIO_D19/LPSPI3_PCS1/CAN0_RX/LPUART1_CTS/LPUART3_RX/EIRQ[6]/WKPU[15]/ADC0_S1858GPIO[7]/LPUART3_TX/LPSPI0_PCS1/eMIOS_1_CH[11]_H/CAN0_TX/LPUART1_RTS/FXIO_D9/EIRQ[7]/ADC0_S1157GPIO[72]/LPI2C0_SCL/CAN1_TX/eMIOS_1_CH[9]_H/LCU1_OUT7/LPSPI0_SCK/FXIO_D12/LPUART0_CTS/LPUART1_RX/EIRQ[16]/ADC0_S1256GPIO[73]/LPI2C0_SDA/LPUART1_TX/LPUART0_RTS/eMIOS_1_CH[8]_X/LCU1_OUT6/LPSPI0_SIN/FXIO_D13/CAN1_RX/EIRQ[17]/ADC0_S13/WKPU[10]55GPIO[32]/LPI2C0_SDAS/FXIO_D14/LPSPI0_PCS0/eMIOS_0_CH[3]_G/LCU1_OUT5/eMIOS_1_CH[6]_H/HSE_TAMPER_LOOP_OUT0/CAN0_RX/LPUART0_RX/EIRQ[8]/ADC1_S14/ADC0_S14/WKPU[7]54GPIO[33]/LPI2C0_SCLS/LPUART0_TX/LPSPI0_SOUT/eMIOS_0_CH[7]_G/CAN0_TX/eMIOS_1_CH[5]_H/LCU1_OUT4/HSE_TAMPER_EXTIN0/EIRQ[9]/ADC1_S15/ADC0_S1553GPIO[74]/eMIOS_0_CH[6]_G/CAN5_TX/LPSPI2_PCS1/LCU1_OUT11/eMIOS_1_CH[0]_X/EIRQ[18]/TRGMUX_IN11/ADC1_X[3]52GPIO[75]/eMIOS_1_CH[1]_H/FXIO_D15/FXIO_D19/LCU1_OUT10/CAN5_RX/EIRQ[19]/TRGMUX_IN10/WKPU[18]/ADC0_S1751
Footprint
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3D Model
No 3D preview

Pin Map

PinNameTypeMountShapeWidth × Height (mm)
GPIO[144]/FCCU_ERR1/LPUART3_TX/LPSPI2_SIN/eMIOS_0_CH[23]_X/LPUART1_RTS/FXIO_D3/TRGMUX_OUT7/FCCU_ERR_IN1/EIRQ[15]/ADC0_P4/WKPU[19]passiveSMDoval1.27×0.254
GPIO[143]/FCCU_ERR0/LPSPI2_SCK/eMIOS_0_CH[22]_X/CMP1_RRT/FXIO_D2/TRGMUX_OUT6/FCCU_ERR_IN0/LPUART1_CTS/LPUART3_RX/EIRQ[14]/ADC0_P3passiveSMDoval1×0.254
GPIO[97]/LPUART5_TX/eMIOS_0_CH[3]_G/LPSPI3_SCK/eMIOS_0_CH[17]_Y/FXIO_D1/TRGMUX_OUT2/EIRQ[9]/ADC0_P0passiveSMDoval1.27×0.254
GPIO[96]/eMIOS_0_CH[2]_G/LPSPI3_SOUT/eMIOS_0_CH[16]_X/FXIO_D0/TRGMUX_OUT1/LPUART5_RX/EIRQ[8]/WKPU[6]/ADC0_P1passiveSMDoval1×0.254
GPIO[139]/LPUART4_TX/LPSPI2_PCS0/eMIOS_0_CH[1]_G/eMIOS_0_CH[21]_Y/FXIO_D5/TRGMUX_OUT5/EIRQ[10]/WKPU[28]/ADC0_P6passiveSMDoval1.27×0.254
GPIO[138]/LPSPI3_SIN/LPSPI2_PCS1/eMIOS_0_CH[20]_Y/CLKOUT_STANDBY/FXIO_D4/TRGMUX_OUT4/LPUART4_RX/EIRQ[9]/ADC0_P5passiveSMDoval1×0.254
GPIO[141]/eMIOS_1_CH[5]_H/LPSPI2_PCS2/LPSPI2_PCS0/FXIO_D5/EIRQ[12]/ADC1_S19passiveSMDoval1.27×0.254
VREFHpassiveSMDoval1×0.254
VREFLpassiveSMDoval1.27×0.254
VDD_HV_ApowerSMDoval1×0.254
V25passiveSMDoval1.27×0.254
VSSgroundSMDoval1×0.254
V11passiveSMDoval1.27×0.254
VSSgroundSMDoval1×0.254
EXTALpassiveSMDoval1.27×0.254
VSSgroundSMDoval1×0.254
XTALpassiveSMDoval1.27×0.254
GPIO[131]/CAN4_TX/eMIOS_0_CH[19]_Y/FXIO_D6/LPUART2_RTS/CMP0_OUT/LPUART5_RX/EIRQ[3]/TRGMUX_IN6passiveSMDoval1×0.254
GPIO[140]/CMP0_RRT/CAN5_TX/LPUART2_TX/eMIOS_1_CH[5]_H/FXIO_D8/FXIO_D7/EIRQ[11]passiveSMDoval1.27×0.254
GPIO[113]/eMIOS_0_CH[18]_Y/LPSPI3_PCS0/FXIO_D9/CAN5_RX/LPUART2_RX/EIRQ[24]passiveSMDoval1×0.254
GPIO[112]/eMIOS_0_CH[1]_G/LPSPI0_SIN/eMIOS_1_CH[15]_H/LPUART2_RTS/CMP0_IN5passiveSMDoval1.27×0.254
GPIO[111]/FXIO_D6/eMIOS_0_CH[0]_X/eMIOS_1_CH[14]_H/LPSPI0_SCK/FXIO_D10/CAN3_RX/LPUART2_CTS/EIRQ[31]/CMP0_IN1passiveSMDoval1×0.254
GPIO[137]/eMIOS_0_CH[7]_G/eMIOS_1_CH[13]_H/CAN3_TX/FXIO_D11/LPUART2_CTS/EIRQ[8]/CMP0_IN0passiveSMDoval1.27×0.254
GPIO[110]/eMIOS_0_CH[21]_Y/LPUART1_TX/LPI2C0_SCL/CMP0_RRT/CLKOUT_RUN/EIRQ[30]passiveSMDoval1×0.254
GPIO[109]/eMIOS_0_CH[20]_Y/FXIO_D7/LPI2C0_SDA/LPUART1_RX/EIRQ[29]/WKPU[24]passiveSMDoval1.27×0.254
GPIO[136]/LPSPI3_PCS1/eMIOS_0_CH[6]_G/FXIO_D12/FXIO_D8/EIRQ[7]/CMP0_IN3passiveSMDoval0.25×1.27
GPIO[37]/eMIOS_0_CH[5]_G/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT_RUN/eMIOS_1_CH[11]_H/EIRQ[13]/TRGMUX_IN0passiveSMDoval0.25×1
GPIO[36]/eMIOS_0_CH[4]_G/LPSPI0_SOUT/eMIOS_1_CH[10]_H/EIRQ[12]/TRGMUX_IN1passiveSMDoval0.25×1.27
GPIO[67]/eMIOS_0_CH[3]_G/CAN0_TX/LPUART0_TX/I3C0_PUR/EIRQ[3]/CMP0_IN4passiveSMDoval0.25×1
GPIO[66]/eMIOS_0_CH[2]_G/LPSPI3_PCS2/LPSPI0_PCS2/CAN0_RX/LPUART0_RX/EIRQ[2]/CMP0_IN2passiveSMDoval0.25×1.27
GPIO[103]/LPUART2_TX/LPSPI3_PCS3/LPSPI0_PCS3/EIRQ[15]/CMP0_IN6passiveSMDoval0.25×1
GPIO[102]/FXIO_D3/eMIOS_1_CH[12]_H/FXIO_D13/LPSPI0_PCS0/LPUART2_RX/EIRQ[14]/CMP0_IN7passiveSMDoval0.25×1.27
GPIO[101]/eMIOS_0_CH[19]_Y/eMIOS_0_CH[2]_G/I3C0_SDA/FXIO_D15/LPSPI0_PCS1/EIRQ[13]/TRGMUX_IN7passiveSMDoval0.25×1
GPIO[108]/eMIOS_0_CH[18]_Y/LPUART2_RTS/LPSPI0_SOUT/LPI2C1_HREQ/EIRQ[28]passiveSMDoval0.25×1.27
GPIO[107]/eMIOS_0_CH[17]_Y/LPSPI0_SCK/LPUART2_CTS/EIRQ[27]passiveSMDoval0.25×1
GPIO[106]/eMIOS_0_CH[16]_X/eMIOS_1_CH[10]_H/LPSPI0_SIN/CLKOUT_RUN/EIRQ[26]passiveSMDoval0.25×1.27
VDD_HV_ApowerSMDoval0.25×1
VSSgroundSMDoval0.25×1.27
GPIO[65]/eMIOS_0_CH[1]_G/FXIO_D5/eMIOS_0_CH[15]_H/CAN3_RX/EIRQ[1]passiveSMDoval0.25×1
GPIO[64]/CAN3_TX/eMIOS_0_CH[0]_X/eMIOS_0_CH[14]_H/EIRQ[0]passiveSMDoval0.25×1.27
GPIO[105]/LPI2C1_SCL/FXIO_D0/LPUART6_TX/I3C0_SCL/eMIOS_0_CH[13]_H/FXIO_D10/EIRQ[25]passiveSMDoval0.25×1
GPIO[104]/LPSPI3_SOUT/LPI2C1_SDA/I3C0_SDA/FXIO_D1/eMIOS_0_CH[12]_H/FXIO_D11/LPUART6_RX/EIRQ[24]passiveSMDoval0.25×1.27
GPIO[81]/LPSPI3_SCK/I3C0_PUR/CAN2_TX/LPI2C1_SCLS/FXIO_D14/FXIO_D2passiveSMDoval0.25×1
GPIO[80]/LPSPI3_SIN/eMIOS_1_CH[9]_H/LPI2C1_SDAS/I3C0_SCL/FXIO_D15/LPI2C1_SDA/CAN2_RX/LPUART2_RXpassiveSMDoval0.25×1.27
GPIO[79]/CAN2_TX/eMIOS_0_CH[11]_H/LPSPI2_SCK/ADC0_MA[2]/LPUART2_TX/LCU1_OUT0/LPI2C1_SCL/EIRQ[23]/TRGMUX_IN8passiveSMDoval0.25×1
GPIO[78]/eMIOS_0_CH[10]_H/LPSPI2_PCS0/ADC0_MA[1]/eMIOS_1_CH[4]_H/LCU1_OUT1/FXIO_D16/CAN2_RX/EIRQ[22]/TRGMUX_IN9passiveSMDoval0.25×1.27
GPIO[35]/eMIOS_0_CH[9]_H/LPSPI2_SOUT/ADC0_MA[0]/CAN4_TX/LCU1_OUT2/FXIO_D17/EIRQ[11]/TRGMUX_IN2passiveSMDoval0.25×1
GPIO[34]/ADC1_MA[0]/eMIOS_0_CH[8]_X/LPSPI2_SIN/LCU1_OUT3/FXIO_D18/CAN4_RX/EIRQ[10]/TRGMUX_IN3/WKPU[8]passiveSMDoval0.25×1.27
GPIO[77]/eMIOS_1_CH[3]_H/eMIOS_0_CH[23]_X/ADC1_MA[1]/FXIO_D16/LCU1_OUT8/EIRQ[21]passiveSMDoval0.25×1
GPIO[76]/ADC1_MA[2]/eMIOS_1_CH[2]_H/eMIOS_0_CH[22]_X/LPSPI2_PCS1/FXIO_D19/LCU1_OUT9/EIRQ[20]passiveSMDoval0.25×1.27
GPIO[75]/eMIOS_1_CH[1]_H/FXIO_D15/FXIO_D19/LCU1_OUT10/CAN5_RX/EIRQ[19]/TRGMUX_IN10/WKPU[18]/ADC0_S17passiveSMDoval1.27×0.254
GPIO[74]/eMIOS_0_CH[6]_G/CAN5_TX/LPSPI2_PCS1/LCU1_OUT11/eMIOS_1_CH[0]_X/EIRQ[18]/TRGMUX_IN11/ADC1_X[3]passiveSMDoval1×0.254
GPIO[33]/LPI2C0_SCLS/LPUART0_TX/LPSPI0_SOUT/eMIOS_0_CH[7]_G/CAN0_TX/eMIOS_1_CH[5]_H/LCU1_OUT4/HSE_TAMPER_EXTIN0/EIRQ[9]/ADC1_S15/ADC0_S15passiveSMDoval1.27×0.254
GPIO[32]/LPI2C0_SDAS/FXIO_D14/LPSPI0_PCS0/eMIOS_0_CH[3]_G/LCU1_OUT5/eMIOS_1_CH[6]_H/HSE_TAMPER_LOOP_OUT0/CAN0_RX/LPUART0_RX/EIRQ[8]/ADC1_S14/ADC0_S14/WKPU[7]passiveSMDoval1×0.254
GPIO[73]/LPI2C0_SDA/LPUART1_TX/LPUART0_RTS/eMIOS_1_CH[8]_X/LCU1_OUT6/LPSPI0_SIN/FXIO_D13/CAN1_RX/EIRQ[17]/ADC0_S13/WKPU[10]passiveSMDoval1.27×0.254
GPIO[72]/LPI2C0_SCL/CAN1_TX/eMIOS_1_CH[9]_H/LCU1_OUT7/LPSPI0_SCK/FXIO_D12/LPUART0_CTS/LPUART1_RX/EIRQ[16]/ADC0_S12passiveSMDoval1×0.254
GPIO[7]/LPUART3_TX/LPSPI0_PCS1/eMIOS_1_CH[11]_H/CAN0_TX/LPUART1_RTS/FXIO_D9/EIRQ[7]/ADC0_S11passiveSMDoval1.27×0.254
GPIO[6]/LPSPI1_PCS1/eMIOS_1_CH[13]_H/FXIO_D19/LPSPI3_PCS1/CAN0_RX/LPUART1_CTS/LPUART3_RX/EIRQ[6]/WKPU[15]/ADC0_S18passiveSMDoval1×0.254
GPIO[135]/eMIOS_0_CH[7]_G/LPSPI3_SCK/FXIO_D11/LPUART4_RXpassiveSMDoval1.27×0.254
V11passiveSMDoval1×0.254
VSSgroundSMDoval1.27×0.254
VDD_HV_ApowerSMDoval1×0.254
GPIO[49]/eMIOS_0_CH[5]_G/LPSPI1_PCS3/eMIOS_1_CH[7]_H/LPSPI3_PCS0/FXIO_D20/LPUART4_RX/EIRQ[31]/ADC1_X[2]/WKPU[14]passiveSMDoval1.27×0.254
GPIO[48]/eMIOS_0_CH[4]_G/LPSPI1_SOUT/LPUART4_TX/FXIO_D21/EIRQ[30]/WKPU[13]/ADC1_S12passiveSMDoval1×0.254
GPIO[47]/eMIOS_0_CH[3]_G/LPSPI1_SIN/LPUART7_TX/FXIO_D22/EIRQ[29]/ADC1_S11/WKPU[33]passiveSMDoval1.27×0.254
GPIO[46]/eMIOS_0_CH[2]_G/LPSPI1_SCK/LCU0_OUT7/FXIO_D23/LPUART7_RX/EIRQ[28]/ADC0_S9/ADC1_S9passiveSMDoval1×0.254
GPIO[45]/LPSPI3_PCS2/eMIOS_0_CH[1]_G/FXIO_D8/LCU0_OUT3/FXIO_D24/EIRQ[27]/ADC0_S8/ADC1_S8/WKPU[11]passiveSMDoval1.27×0.254
GPIO[44]/LPSPI3_PCS3/eMIOS_0_CH[0]_X/LCU0_OUT2/FXIO_D25/EIRQ[26]/ADC1_X[1]/WKPU[12]passiveSMDoval1×0.254
GPIO[100]/eMIOS_1_CH[23]_X/LPSPI1_PCS1/LCU0_OUT6/EIRQ[12]/ADC0_S19/WKPU[22]passiveSMDoval1.27×0.254
GPIO[99]/eMIOS_1_CH[22]_X/LPSPI1_PCS0/FXIO_D5/FXIO_D7/LCU0_OUT0/LPUART3_RX/EIRQ[11]/TRGMUX_IN4/NMI_b/WKPU[1]/ADC0_S10passiveSMDoval1×0.254
GPIO[98]/LCU0_OUT1/eMIOS_1_CH[21]_Y/LPSPI1_SOUT/FXIO_D4/FXIO_D6/LPUART3_TX/EIRQ[10]/TRGMUX_IN5/WKPU[9]/ADC0_S16passiveSMDoval1.27×0.254
GPIO[3]/FCCU_ERR1/eMIOS_1_CH[20]_Y/LPSPI1_SCK/LCU0_OUT2/FXIO_D5/LPUART0_TX/FCCU_ERR_IN1/EIRQ[3]/ADC1_S17passiveSMDoval1×0.254
GPIO[2]/FCCU_ERR0/eMIOS_1_CH[19]_Y/FXIO_D4/LCU0_OUT3/FCCU_ERR_IN0/LPSPI1_SIN/LPUART0_RX/EIRQ[2]/ADC1_X[0]/WKPU[0]/CMP1_IN2passiveSMDoval1.27×0.254
GPIO[43]/eMIOS_1_CH[18]_Y/LCU0_OUT8/FXIO_D26/LPI2C0_HREQ/EIRQ[25]/ADC0_X[3]/WKPU[16]passiveSMDoval1×0.254
GPIO[42]/eMIOS_1_CH[17]_Y/LCU0_OUT9/FXIO_D27/EIRQ[24]/ADC0_X[2]passiveSMDoval1.27×0.254
GPIO[41]/eMIOS_1_CH[16]_X/LCU0_OUT10/FXIO_D28/EIRQ[15]/ADC0_X[1]/WKPU[17]passiveSMDoval0.25×1.27
GPIO[40]/eMIOS_1_CH[15]_H/LCU0_OUT11/LPSPI0_PCS5/FXIO_D29/EIRQ[14]/ADC0_X[0]/WKPU[25]passiveSMDoval0.25×1
GPIO[1]/eMIOS_0_CH[9]_H/LPUART0_RTS/FXIO_D3/LCU0_OUT5/LPSPI0_PCS6/TRGMUX_OUT0/EIRQ[1]/ADC0_S9/CMP1_IN1/WKPU[5]passiveSMDoval0.25×1.27
GPIO[0]/eMIOS_0_CH[17]_Y/LCU0_OUT4/FXIO_D2/eMIOS_1_CH[0]_X/LPSPI0_PCS7/TRGMUX_OUT3/LPUART0_CTS/EIRQ[0]/ADC0_S8/CMP1_IN0passiveSMDoval0.25×1
GPIO[71]/FXIO_D10/LPUART1_TX/LPI2C1_SCL/LCU0_OUT6/eMIOS_1_CH[7]_H/LPSPI0_PCS0/CAN2_TX/LPI2C0_HREQ/EIRQ[7]/WKPU[2]/ADC1_S16passiveSMDoval0.25×1.27
GPIO[70]/LPI2C1_SDA/FXIO_D11/LPSPI1_PCS1/LCU0_OUT7/eMIOS_1_CH[6]_H/LPSPI0_PCS1/ADC0_MA[2]/CAN2_RX/LPUART1_RX/EIRQ[6]/WKPU[3]/ADC1_S18passiveSMDoval0.25×1
GPIO[16]/eMIOS_0_CH[11]_H/LPSPI1_PCS2/LPSPI0_PCS4/LPUART6_TX/FXIO_D30/EIRQ[4]/ADC1_S13/WKPU[31]passiveSMDoval0.25×1.27
GPIO[15]/eMIOS_0_CH[10]_H/LPSPI0_PCS3/LPSPI2_PCS3/FXIO_D31/LPUART6_RX/EIRQ[23]/ADC1_P7/WKPU[20]passiveSMDoval0.25×1
GPIO[134]/LPSPI0_PCS2/LPUART1_RTS/eMIOS_1_CH[14]_H/FXIO_D12/ADC0_MA[1]/EIRQ[6]/ADC1_P6/WKPU[29]passiveSMDoval0.25×1.27
GPIO[130]/LPSPI0_SOUT/eMIOS_0_CH[3]_G/eMIOS_1_CH[8]_X/FXIO_D13/ADC0_MA[0]/LPUART1_CTS/EIRQ[2]/WKPU[27]/ADC1_P5passiveSMDoval0.25×1
VSSgroundSMDoval0.25×1.27
VDD_HV_ApowerSMDoval0.25×1
GPIO[14]/eMIOS_1_CH[4]_H/LPSPI1_PCS3/FXIO_D14/EIRQ[22]/ADC1_P4passiveSMDoval0.25×1.27
GPIO[13]/LPSPI1_PCS4/eMIOS_0_CH[15]_H/FXIO_D8/eMIOS_1_CH[3]_H/EIRQ[21]/WKPU[4]/ADC1_P1passiveSMDoval0.25×1
GPIO[12]/LPSPI1_PCS5/eMIOS_0_CH[14]_H/CLKOUT_STANDBY/FXIO_D9/eMIOS_1_CH[2]_H/CMP1_OUT/CAN1_RX/EIRQ[20]/ADC1_P0passiveSMDoval0.25×1.27
GPIO[11]/CAN1_TX/eMIOS_0_CH[13]_H/eMIOS_1_CH[1]_H/FXIO_D1/CMP0_RRT/LPSPI1_PCS0/EIRQ[19]/ADC1_S10passiveSMDoval0.25×1
GPIO[10]/eMIOS_0_CH[12]_H/FXIO_D0/JTAG_TDO/TRACEnoETM_SWO/EIRQ[18]passiveSMDoval0.25×1.27
GPIO[129]/LPSPI0_SCK/FXIO_D2/LPUART7_TX/EIRQ[1]/ADC1_P3passiveSMDoval0.25×1
GPIO[128]/LPSPI0_SIN/FXIO_D3/LPUART7_RX/EIRQ[0]/WKPU[26]/ADC1_P2passiveSMDoval0.25×1.27
GPIO[69]/eMIOS_0_CH[16]_X/FXIO_D4/JTAG_TDI/LPI2C1_HREQ/EIRQ[5]/ADC1_S14passiveSMDoval0.25×1
GPIO[68]/eMIOS_0_CH[8]_X/FXIO_D5/JTAG_TCK/SWD_CLK/EIRQ[4]/CMP1_IN3passiveSMDoval0.25×1.27
GPIO[5]/RESET_b/EIRQ[5]passiveSMDoval0.25×1
GPIO[4]/FXIO_D6/CMP0_OUT/JTAG_TMS/SWD_DIO/EIRQ[4]/ADC1_S15passiveSMDoval0.25×1.27
GPIO[9]/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/LPSPI3_PCS0/EIRQ[17]/WKPU[21]/ADC0_P7passiveSMDoval0.25×1
GPIO[8]/eMIOS_1_CH[12]_H/LPSPI2_SOUT/FXIO_D6/LPUART2_RX/EIRQ[16]/WKPU[23]/ADC0_P2passiveSMDoval0.25×1.27

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Details

Category
ic
MPN
MWCT2016SHVPAR
Manufacturer
NXP Semicon
Package
-
Footprint
MQFP-100_L10.0-W10.0-P0.65-LS12.9-TL
JLCPCB
C20234268
LCSC
C20234268
Lifecycle
active
Mounting
SMT
RoHS
Compliant
ECCN
5A992C

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