microcontroller

LKS32MC457RCT8

Symbol
P0_1/MCPWM1_BKIN2/UART0_RXD/SPI0_CSN/TIM4_CH1/CAN_TX/5VT/EXTI11P0_2/CMP5_OUT/MCPWM1_BKIN3/UART0_TXD/CAN_RX/CMP5_IP0/5VT/FLT/EXTI2/WAKE02NC3P0_3/HALL1_IN2/SPI0_DI/QEP0_Z/CMP5_IP1/FLT/EXTI3/WAKE14P0_4/HALL1_IN1/MCPWM1_BKIN0/UART0_RXD/SPI0_DO/SDA0/TIM0_CH0/QEP0_CH0/QEP3_Z/ADC_TRIGGER1/CAN_TMR/ADC2_CH13/CMP5_IP2/5VT/FLT/EXTI4/WAKE25P0_6/RST_n/5VT6P0_7/OSC_OUT7VSS8P0_8/QEP1_Z/EFLS_DAT[0]/OSC_IN9NC10P3_9/MCPWM0_BKIN0/TIM0_CH1/QEP0_CH1/OPA2_IN/ADC2_CH911P0_9/CMP4_OUT/MCPWM1_CH0N/SPI0_CLK/TIM1_CH0/QEP1_CH0/EFLS_DAT[1]/CMP5_IN/nTRST/FLT12P0_10/MCPWM1_CH0P/SPI0_CSN/TIM1_CH1/QEP1_CH1/EFLS_DAT[2]/CMP4_IN/SWDIO/TMS/5VT/FLT13P0_11/MCPWM1_CH1N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/EFLS_DAT[3]/CMP4_IP0/TDI/5VT/FLT14P0_12/MCPWM1_CH1P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_TMR/EFLS_CSN/CMP4_IP1/SWCLK/TCLK/5VT/FLT15P0_13/MCPWM1_CH2N/UART0_TXD/SPI1_CSN/TIM4_CH0/C16P0_14/CLK/MCPWM1_CH2P/UART0_RXD/SPI1_DI/SCL0/CAN_RX/CMP4_IP3/EXTI717P0_15/CMP4_OUT/MCPWM1_CH3N/QEP1_Z/EXTI818P1_0/MCPWM1_CH3P/UART0_TXD/SPI1_DO/SDA0/QEP0_Z19NC20P0_5/CMP5_OUT/HALL1_IN0/MCPWM0_BKIN3/UART0_TXD/SPI0_CLK/SCL0/TIM0_CH1/QEP0_CH1/QEP2_Z/ADC_TRIGGER0/ADC2_CH12/CMP5_IP3/5VT/FLT/EXTI5/WAKE321VSS22P1_8/MCPWM0_CH3P/UART2_RXD/SPI1_CLK/TIM0_CH0/QEP0_CH0/QEP2_Z/CAN_TMR/5VT/FLT23P1_9/MCPWM0_BKIN0/UART2_TXD/SPI1_DO/SDA0/TIM0_CH1/QEP0_CH1/TIM2_CH0/QEP0_CH0/ADC_TRIGGER2/CAN_TX/5VT/FLT24P1_10/MCPWM0_BKIN1/UART2_RXD/SPI1_DI/SCL0/TIM0_CH0/QEP0_CH0/TIM2_CH1/QEP0_CH1/ADC_TRIGGER1/CAN_RX/5VT/FLT25P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/QEP0_CH1/OPA5_IN/EXTI11/WAKE526P2_3/MCPWM1_CH2P/TIM1_CH1/QEP1_CH1/CAN_TX/EFLS_DAT[3]27P2_4/MCPWM1_CH1P/TIM2_CH0/QEP0_CH0/CAN_RX/EFLS_CSN28P2_5/MCPWM1_CH0P/UART1_RXD/TIM1_CH0/QEP1_CH0/TIM2_CH1/QEP0_CH1/CAN_TMR/EFLS_CLK29P2_6/MCPWM1_CH2N/UART1_TXD/TIM1_CH1/QEP1_CH130P2_7/MCPWM1_CH1N/SDA0/TIM2_CH0/QEP0_CH0/EXTI1631P2_8/MCPWM1_CH0N/SCL0/TIM2_CH1/QEP0_CH1/EXTI1732P4_15/HALL0_IN0/UART2_RXD/SPI1_D1/SCL0/TIM1_CH0/QEP1_CH0/TIM2_CH1/QEP0_CH1/ADC_TRIGGER1/CAN_TMR/EFLS_DAT[2]/ADC0_CH8/CMP0_IP3/5VT/FLT64P4_14/CLK/HALL0_IN1/UART2_TXD/SPI1_DO/SDA0/TIM1_CH1/QEP1_CH1/TIM2_CH0/QEP0_CH0/ADC_TRIGGER2/CAN_RX/EFLS_DAT[1]/ADC0_CH9/CMP0_IP2/5VT/FLT63P5_1/MCPWM0_CH3P/SPI1_CSN/SCL1/TIM4_CH1/TIM3_CH1/QEP1_CH1/EFLS_CSN/ADC0_CH6/FLT/EXTI3362P5_0/CMP0_OUT/MCPWM0_CH3N/SDA1/TIM3_CH0/QEP1_CH0/ADC_TRIGGER0/EFLS_DAT[3]/ADC0_CH7/CMP0_IN/FLT/EXTI3261VSS3360VSS3359AVDD58AVDD57P4_6/MCPWM0_CH1N/EFLS_CLK/ADC1_CH8/OPAx_OUT1/LDO12/P4_7/ADC1_CH7/DAC1_OUT56P4_2/MCPWM0_CH3P/UART0_RXD/SCL0/TIM0_CH0/QEP0_CH0/ADC_TRIGGER2/CAN_TMR/EFLS_DAT[2]/ADC1_CH9/5VT/FLT/EXTI3155P4_1/MCPWM0_CH3N/UART0_TXD/SDA0/TIM0_CH1/QEP0_CH1/EFLS_DAT[1]/ADC1_CH10/5VT/FLT/EXTI3054P3_14/OPA1_IP/ADC2_CH4/EXTI2753P3_13/OPA1_IN/ADC2_CH5/EXTI2652P3_12/MCPWM0_BKIN3/SDA0/TIM2_CH1/QEP0_CH1/ADC2_CH6/EXTI2551P3_11/MCPWM0_BKIN2/ADC2_CH7/OPAx_OUT0/REF/EXTI2450P3_10/MCPWM0_BKIN1/OPA2_IP/ADC2_CH849P3_7/CMP2_OUT/MCPWM1_BKIN0/TIM4_CH1/ADC_TRIGGER1/CAN_RX/OPA3_IN/ADC2_CH11/CMP2_IN/FLT/EXTI2248P3_6/HALL0_IN2/MCPWM1_BKIN3/UART1_TXD/SPI0_DI/TIM1_CH1/QEP1_CH1/ADC_TRIGGER2/CAN_TX/EFLS_CSN/CMP2_IP3/5VT47P3_4/HALL0_IN0/SPI0_CLK/TIM1_CH1/QEP1_CH1/EFLS_DAT[2]/ADC1_CH12/DAC0_OUT/CMP2_IP1/5VT46P3_3/CMP2_OUT/SPI0_CSN/TIM0_CH1/QEP0_CH1/EFLS_DAT[1]45VSS44P3_2/CMP3_OUT/HALL1_IN0/SCL0/TIM0_CH0/QEP0_CH0/TIM3_CH0/QEP1_CH0/EFLS_DAT[0]/CMP3_IP3/5VT/EXTI20/WAKE743NC42P3_1/HALL1_IN1/MCPWM0_BKIN3/SDA0/QEP0_Z/TIM3_CH0/QEP1_CH0/ADC0_CH13/CMP3_IP2/5VT41P3_0/HALL1_IN2/MCPWM0_CH2N/QEP3_Z/ADC0_CH14/CMP3_IP1/5VT40P2_15/CMP3_OUT/HALL0_IN0/MCPWM0_BKIN0/UART2_RXD/TIM1_CH0/QEP1_CH0/EFLS_CLK/CMP3_IP0/5VT/39P2_14/HALL0_IN1/MCPWM0_CH0N/UART2_TXD/TIM3_CH1/QEP1_CH1/ADC_TRIGGER0/CMP3_IN/WAKE638P2_13/HALL0_IN2/MCPWM0_CH1N/TIM4_CH0/TIM3_CH0/QEP1_CH0/ADC_TRIGGER1/EFLS_CSN37P2_12/MCPWM0_CH2N/UART0_TXD/TIM4_CH1/QEP3_Z/EFLS_DAT[3]/5VT/EXTI1836P2_11/MCPWM0_CH0P/UART0_RXD/TIM4_CH0/TIM3_CH1/QEP1_CH1/EFLS_DAT[2]/5VT35P2_10/MCPWM0_CH1P/SCL0/TIM4_CH0/EFLS_DAT[1]34P2_9/MCPWM0_CH2P/SDA0/TIM4_CH1/QEP2_Z/EFLS_DAT[033
Footprint
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
3D Model
Pin Map
PinNameTypeMountShapeWidth × Height (mm)
P0_1/MCPWM1_BKIN2/UART0_RXD/SPI0_CSN/TIM4_CH1/CAN_TX/5VT/EXTI1inputSMDoval0.3×1.5
P0_2/CMP5_OUT/MCPWM1_BKIN3/UART0_TXD/CAN_RX/CMP5_IP0/5VT/FLT/EXTI2/WAKE0outputSMDoval0.3×1.5
NCncSMDoval0.3×1.5
P0_3/HALL1_IN2/SPI0_DI/QEP0_Z/CMP5_IP1/FLT/EXTI3/WAKE1passiveSMDoval0.3×1.5
P0_4/HALL1_IN1/MCPWM1_BKIN0/UART0_RXD/SPI0_DO/SDA0/TIM0_CH0/QEP0_CH0/QEP3_Z/ADC_TRIGGER1/CAN_TMR/ADC2_CH13/CMP5_IP2/5VT/FLT/EXTI4/WAKE2passiveSMDoval0.3×1.5
P0_6/RST_n/5VTpassiveSMDoval0.3×1.5
P0_7/OSC_OUTpassiveSMDoval0.3×1.5
VSSgroundSMDoval0.3×1.5
P0_8/QEP1_Z/EFLS_DAT[0]/OSC_INpassiveSMDoval0.3×1.5
NCncSMDoval0.3×1.5
P3_9/MCPWM0_BKIN0/TIM0_CH1/QEP0_CH1/OPA2_IN/ADC2_CH9passiveSMDoval0.3×1.5
P0_9/CMP4_OUT/MCPWM1_CH0N/SPI0_CLK/TIM1_CH0/QEP1_CH0/EFLS_DAT[1]/CMP5_IN/nTRST/FLTpassiveSMDoval0.3×1.5
P0_10/MCPWM1_CH0P/SPI0_CSN/TIM1_CH1/QEP1_CH1/EFLS_DAT[2]/CMP4_IN/SWDIO/TMS/5VT/FLTpassiveSMDoval0.3×1.5
P0_11/MCPWM1_CH1N/UART1_RXD/SPI0_DI/SCL1/TIM4_CH1/EFLS_DAT[3]/CMP4_IP0/TDI/5VT/FLTpassiveSMDoval0.3×1.5
P0_12/MCPWM1_CH1P/UART1_TXD/SPI0_DO/SDA1/TIM4_CH0/CAN_TMR/EFLS_CSN/CMP4_IP1/SWCLK/TCLK/5VT/FLTpassiveSMDoval0.3×1.5
P0_13/MCPWM1_CH2N/UART0_TXD/SPI1_CSN/TIM4_CH0/CpassiveSMDoval0.3×1.5
P0_14/CLK/MCPWM1_CH2P/UART0_RXD/SPI1_DI/SCL0/CAN_RX/CMP4_IP3/EXTI7passiveSMDoval1.5×0.3
P0_15/CMP4_OUT/MCPWM1_CH3N/QEP1_Z/EXTI8passiveSMDoval1.5×0.3
P1_0/MCPWM1_CH3P/UART0_TXD/SPI1_DO/SDA0/QEP0_ZpassiveSMDoval1.5×0.3
NCncSMDoval1.5×0.3
P0_5/CMP5_OUT/HALL1_IN0/MCPWM0_BKIN3/UART0_TXD/SPI0_CLK/SCL0/TIM0_CH1/QEP0_CH1/QEP2_Z/ADC_TRIGGER0/ADC2_CH12/CMP5_IP3/5VT/FLT/EXTI5/WAKE3passiveSMDoval1.5×0.3
VSSgroundSMDoval1.5×0.3
P1_8/MCPWM0_CH3P/UART2_RXD/SPI1_CLK/TIM0_CH0/QEP0_CH0/QEP2_Z/CAN_TMR/5VT/FLTpassiveSMDoval1.5×0.3
P1_9/MCPWM0_BKIN0/UART2_TXD/SPI1_DO/SDA0/TIM0_CH1/QEP0_CH1/TIM2_CH0/QEP0_CH0/ADC_TRIGGER2/CAN_TX/5VT/FLTpassiveSMDoval1.5×0.3
P1_10/MCPWM0_BKIN1/UART2_RXD/SPI1_DI/SCL0/TIM0_CH0/QEP0_CH0/TIM2_CH1/QEP0_CH1/ADC_TRIGGER1/CAN_RX/5VT/FLTpassiveSMDoval1.5×0.3
P1_11/MCPWM0_BKIN2/UART2_TXD/SPI0_DO/SDA0/TIM0_CH1/QEP0_CH1/OPA5_IN/EXTI11/WAKE5passiveSMDoval1.5×0.3
P2_3/MCPWM1_CH2P/TIM1_CH1/QEP1_CH1/CAN_TX/EFLS_DAT[3]passiveSMDoval1.5×0.3
P2_4/MCPWM1_CH1P/TIM2_CH0/QEP0_CH0/CAN_RX/EFLS_CSNpassiveSMDoval1.5×0.3
P2_5/MCPWM1_CH0P/UART1_RXD/TIM1_CH0/QEP1_CH0/TIM2_CH1/QEP0_CH1/CAN_TMR/EFLS_CLKpassiveSMDoval1.5×0.3
P2_6/MCPWM1_CH2N/UART1_TXD/TIM1_CH1/QEP1_CH1passiveSMDoval1.5×0.3
P2_7/MCPWM1_CH1N/SDA0/TIM2_CH0/QEP0_CH0/EXTI16passiveSMDoval1.5×0.3
P2_8/MCPWM1_CH0N/SCL0/TIM2_CH1/QEP0_CH1/EXTI17passiveSMDoval1.5×0.3
P2_9/MCPWM0_CH2P/SDA0/TIM4_CH1/QEP2_Z/EFLS_DAT[0passiveSMDoval0.3×1.5
P2_10/MCPWM0_CH1P/SCL0/TIM4_CH0/EFLS_DAT[1]passiveSMDoval0.3×1.5
P2_11/MCPWM0_CH0P/UART0_RXD/TIM4_CH0/TIM3_CH1/QEP1_CH1/EFLS_DAT[2]/5VTpassiveSMDoval0.3×1.5
P2_12/MCPWM0_CH2N/UART0_TXD/TIM4_CH1/QEP3_Z/EFLS_DAT[3]/5VT/EXTI18passiveSMDoval0.3×1.5
P2_13/HALL0_IN2/MCPWM0_CH1N/TIM4_CH0/TIM3_CH0/QEP1_CH0/ADC_TRIGGER1/EFLS_CSNpassiveSMDoval0.3×1.5
P2_14/HALL0_IN1/MCPWM0_CH0N/UART2_TXD/TIM3_CH1/QEP1_CH1/ADC_TRIGGER0/CMP3_IN/WAKE6passiveSMDoval0.3×1.5
P2_15/CMP3_OUT/HALL0_IN0/MCPWM0_BKIN0/UART2_RXD/TIM1_CH0/QEP1_CH0/EFLS_CLK/CMP3_IP0/5VT/passiveSMDoval0.3×1.5
P3_0/HALL1_IN2/MCPWM0_CH2N/QEP3_Z/ADC0_CH14/CMP3_IP1/5VTpassiveSMDoval0.3×1.5
P3_1/HALL1_IN1/MCPWM0_BKIN3/SDA0/QEP0_Z/TIM3_CH0/QEP1_CH0/ADC0_CH13/CMP3_IP2/5VTpassiveSMDoval0.3×1.5
NCncSMDoval0.3×1.5
P3_2/CMP3_OUT/HALL1_IN0/SCL0/TIM0_CH0/QEP0_CH0/TIM3_CH0/QEP1_CH0/EFLS_DAT[0]/CMP3_IP3/5VT/EXTI20/WAKE7passiveSMDoval0.3×1.5
VSSgroundSMDoval0.3×1.5
P3_3/CMP2_OUT/SPI0_CSN/TIM0_CH1/QEP0_CH1/EFLS_DAT[1]passiveSMDoval0.3×1.5
P3_4/HALL0_IN0/SPI0_CLK/TIM1_CH1/QEP1_CH1/EFLS_DAT[2]/ADC1_CH12/DAC0_OUT/CMP2_IP1/5VTpassiveSMDoval0.3×1.5
P3_6/HALL0_IN2/MCPWM1_BKIN3/UART1_TXD/SPI0_DI/TIM1_CH1/QEP1_CH1/ADC_TRIGGER2/CAN_TX/EFLS_CSN/CMP2_IP3/5VTpassiveSMDoval0.3×1.5
P3_7/CMP2_OUT/MCPWM1_BKIN0/TIM4_CH1/ADC_TRIGGER1/CAN_RX/OPA3_IN/ADC2_CH11/CMP2_IN/FLT/EXTI22passiveSMDoval0.3×1.5
P3_10/MCPWM0_BKIN1/OPA2_IP/ADC2_CH8passiveSMDoval1.5×0.3
P3_11/MCPWM0_BKIN2/ADC2_CH7/OPAx_OUT0/REF/EXTI24passiveSMDoval1.5×0.3
P3_12/MCPWM0_BKIN3/SDA0/TIM2_CH1/QEP0_CH1/ADC2_CH6/EXTI25passiveSMDoval1.5×0.3
P3_13/OPA1_IN/ADC2_CH5/EXTI26passiveSMDoval1.5×0.3
P3_14/OPA1_IP/ADC2_CH4/EXTI27passiveSMDoval1.5×0.3
P4_1/MCPWM0_CH3N/UART0_TXD/SDA0/TIM0_CH1/QEP0_CH1/EFLS_DAT[1]/ADC1_CH10/5VT/FLT/EXTI30passiveSMDoval1.5×0.3
P4_2/MCPWM0_CH3P/UART0_RXD/SCL0/TIM0_CH0/QEP0_CH0/ADC_TRIGGER2/CAN_TMR/EFLS_DAT[2]/ADC1_CH9/5VT/FLT/EXTI31passiveSMDoval1.5×0.3
P4_6/MCPWM0_CH1N/EFLS_CLK/ADC1_CH8/OPAx_OUT1/LDO12/P4_7/ADC1_CH7/DAC1_OUTpassiveSMDoval1.5×0.3
AVDDpowerSMDoval1.5×0.3
AVDDpowerSMDoval1.5×0.3
VSS33passiveSMDoval1.5×0.3
VSS33passiveSMDoval1.5×0.3
P5_0/CMP0_OUT/MCPWM0_CH3N/SDA1/TIM3_CH0/QEP1_CH0/ADC_TRIGGER0/EFLS_DAT[3]/ADC0_CH7/CMP0_IN/FLT/EXTI32passiveSMDoval1.5×0.3
P5_1/MCPWM0_CH3P/SPI1_CSN/SCL1/TIM4_CH1/TIM3_CH1/QEP1_CH1/EFLS_CSN/ADC0_CH6/FLT/EXTI33passiveSMDoval1.5×0.3
P4_14/CLK/HALL0_IN1/UART2_TXD/SPI1_DO/SDA0/TIM1_CH1/QEP1_CH1/TIM2_CH0/QEP0_CH0/ADC_TRIGGER2/CAN_RX/EFLS_DAT[1]/ADC0_CH9/CMP0_IP2/5VT/FLTpassiveSMDoval1.5×0.3
P4_15/HALL0_IN0/UART2_RXD/SPI1_D1/SCL0/TIM1_CH0/QEP1_CH0/TIM2_CH1/QEP0_CH1/ADC_TRIGGER1/CAN_TMR/EFLS_DAT[2]/ADC0_CH8/CMP0_IP3/5VT/FLTpassiveSMDoval1.5×0.3

Key Parameters

Frequency
192MHz

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Details

Category
microcontroller
MPN
LKS32MC457RCT8
Manufacturer
LINKOSEMI
Package
LQFP-64(10x10)
Footprint
LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL
JLCPCB
C22469874
LCSC
C22469874
Lifecycle
active
Mounting
SMT
RoHS
Compliant
MSL
MSL 3
ECCN
-

JLCPCB Stock & Pricing

In Stock(474 pcs)
1-9 pcs$2.4241
10-29 pcs$2.2956
30-159 pcs$2.2201
160-479 pcs$2.1430
480-959 pcs$2.1077
960+ pcs$2.0916