microcontroller

FS32K148HAT0VLQT

Symbol
PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT71PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT62PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT23PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/TRACE_D0/FXIO_D0/TRGMUX_OUT14PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT55PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT46PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT07PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN8PTE4/TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/*EWM_OUT9PTA25/FTM5_CH010VDD111VSS112VDDA13VREFH14VREFL15VSS216PTB7/LPI2C0_SCL/EXTAL17PTB6/LPI2C0_SDA/XTAL18PTA26/FTM5_CH1/LPSPI1_PCS0/LPSPI0_PCS019PTE14/FTM0_FLT1/FTM2_FLT120PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT21PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX/CAN0_TX22PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT023PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX/CAN0_RX24PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT125PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SIN26PTA30/FTM5_CH5/LPUART2_RX/LPSPI0_SOUT27PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/CMP0_RRT/TRACE_CLKOUT28PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR229PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR330VSS331VDD232PTA31/FTM5_CH6/LPSPI0_PCS133PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUT34PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUT35PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE1636PTB20/FTM6_CH0/ADC0_SE1737PTB21/FTM6_CH1/ADC0_SE1838PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN339PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDC40PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO041PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN442PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD[0]/TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CMP0_IN543PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD[1]/TRACE_D0/QSPI_A_IO1/CMP0_IN644PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN745PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO246PTD12/FTM2_CH2/LPI2C1_HREQ/TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO247PTD11/FTM2_CH1/FTM2_QD_PHA/TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO048PTD10/FTM2_CH0/FTM2_QD_PHB/TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCK49VSS450VDD351PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH7/QSPI_B_SCK/ADC0_SE952PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH6/QSPI_B_RWDS/ADC0_SE853PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO454PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO555PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE1556PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE1457PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE1958PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE1359PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE2060PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE1261PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE2162PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE763PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE2264PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE2365VSS566VDD467PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE668PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE2469PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTS70PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTS71PTC19/FTM7_CH5/LPSPI2_PCS1/ADC0_SE2572PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1144PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT0143PTA4/CMP0_OUT/*EWM_OUT/JTAG_TMS/SWD_DIO142PTA5/TCLK1/*RESET141PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2140PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDI139PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D2138PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D1137PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO136PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNC135PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLK134PTE25/FTM4_CH5/CAN2_RX/ADC1_SE31133PTE24/FTM4_CH4/CAN2_TX/ADC1_SE30132PTE23/FTM4_CH3/ADC1_SE29131PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D0130PTE22/FTM4_CH2/ADC1_SE28129PTE21/FTM4_CH1/ADC1_SE27128PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D3127PTE20/FTM4_CH0/ADC1_SE26126PTE19/FTM7_CH7/ADC1_SE25125VDD6124VSS7123PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE10122PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11121PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE12120PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE13119PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4118PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5117PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24116PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0115PTD29/FTM7_CH2/ADC1_SE23114PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1113PTD28/FTM7_CH1/ADC1_SE22112PTB8/FTM3_CH0/SAI1_BCLK111PTD27/FTM7_CH0/ADC1_SE21110PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D0109PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLK108PTB11/FTM3_CH3/LPI2C0_HREQ107PTD24/FTM6_CH5/ADC1_SE20106PTA2/FTM3_CH0/LPI2C0_SDA/*EWM_OUT/FXIO_D4/LPUART0_RX/ADC1_SE0105PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1104PTD23/FTM6_CH4/ADC1_SE19103PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2102PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/*NMI/ADC1_SE3101PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6100PTD22/FTM6_CH3/ADC1_SE1899PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE798PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE897PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE996PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE1495PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE1594PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT193PTA17/FTM0_CH6/FTM3_FLT0/*EWM_OUT/FTM5_FLT092VDD591VSS690PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE1789PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE1688PTE7/FTM0_CH7/FTM3_FLT087PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/ADC0_SE3186PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE285PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/ADC0_SE3084PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE383PTC29/FTM5_CH2/ADC0_SE2982PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTS81PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTS80PTC28/FTM4_CH7/ADC0_SE2879PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE1478PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE1577PTC27/FTM4_CH4/ADC0_SE2776PTC10/FTM3_CH4/TRGMUX_IN1175PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN1074PTC23/LPSPI0_SCK/ADC0_SE2673
Footprint
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3D Model
Pin Map
PinNameTypeMountShapeWidth × Height (mm)
PTE16/LPUART1_RTS/LPSPI2_SIN/FTM2_CH7/FTM4_FLT0/FXIO_D3/TRGMUX_OUT7inputSMDoval0.28×2
PTE15/LPUART1_CTS/LPSPI2_SCK/FTM2_CH6/FTM4_FLT1/FXIO_D2/TRGMUX_OUT6outputSMDoval0.28×2
PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/SAI0_MCLK/FXIO_D1/TRGMUX_OUT2ioSMDoval0.28×2
PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/TRACE_D0/FXIO_D0/TRGMUX_OUT1passiveSMDoval0.28×2
PTE11/LPSPI2_PCS0/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5passiveSMDoval0.28×2
PTE10/CLKOUT/LPSPI2_PCS1/FTM2_CH4/FXIO_D4/TRGMUX_OUT4passiveSMDoval0.28×2
PTE13/FTM4_CH5/LPSPI2_PCS2/FTM2_FLT0passiveSMDoval0.28×2
PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_INpassiveSMDoval0.28×2
PTE4/TRACE_D1/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/*EWM_OUTpassiveSMDoval0.28×2
PTA25/FTM5_CH0passiveSMDoval0.28×2
VDD1passiveSMDoval0.28×2
VSS1passiveSMDoval0.28×2
VDDApowerSMDoval0.28×2
VREFHpassiveSMDoval0.28×2
VREFLpassiveSMDoval0.28×2
VSS2passiveSMDoval0.28×2
PTB7/LPI2C0_SCL/EXTALpassiveSMDoval0.28×2
PTB6/LPI2C0_SDA/XTALpassiveSMDoval0.28×2
PTA26/FTM5_CH1/LPSPI1_PCS0/LPSPI0_PCS0passiveSMDoval0.28×2
PTE14/FTM0_FLT1/FTM2_FLT1passiveSMDoval0.28×2
PTE3/FTM0_FLT0/LPUART2_RTS/FTM2_FLT0/TRGMUX_IN6/CMP0_OUTpassiveSMDoval0.28×2
PTA27/FTM5_CH2/LPSPI1_SOUT/LPUART0_TX/CAN0_TXpassiveSMDoval0.28×2
PTE12/FTM0_FLT3/LPUART2_TX/FTM5_FLT0passiveSMDoval0.28×2
PTA28/FTM5_CH3/LPSPI1_SCK/LPUART0_RX/CAN0_RXpassiveSMDoval0.28×2
PTD17/FTM0_FLT2/LPUART2_RX/FTM5_FLT1passiveSMDoval0.28×2
PTA29/FTM5_CH4/LPUART2_TX/LPSPI1_SINpassiveSMDoval0.28×2
PTA30/FTM5_CH5/LPUART2_RX/LPSPI0_SOUTpassiveSMDoval0.28×2
PTD16/FTM0_CH1/TRACE_D2/LPSPI0_SIN/CMP0_RRT/TRACE_CLKOUTpassiveSMDoval0.28×2
PTD15/FTM0_CH0/TRACE_D3/LPSPI0_SCK/ENET_TMR2passiveSMDoval0.28×2
PTE9/FTM0_CH7/LPUART2_CTS/ENET_TMR3passiveSMDoval0.28×2
VSS3passiveSMDoval0.28×2
VDD2passiveSMDoval0.28×2
PTA31/FTM5_CH6/LPSPI0_PCS1passiveSMDoval0.28×2
PTD14/FTM2_CH5/LPUART1_TX/ENET_TMR0/CLKOUTpassiveSMDoval0.28×2
PTD13/FTM2_CH4/LPUART1_RX/ENET_TMR1/RTC_CLKOUTpassiveSMDoval0.28×2
PTB18/FTM5_CH7/LPSPI1_PCS1/ADC0_SE16passiveSMDoval0.28×2
PTB20/FTM6_CH0/ADC0_SE17passiveSMDoval2×0.28
PTB21/FTM6_CH1/ADC0_SE18passiveSMDoval2×0.28
PTE8/FTM0_CH6/MII_RMII_MDC/CMP0_IN3passiveSMDoval2×0.28
PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0/MII_RMII_MDCpassiveSMDoval2×0.28
PTB4/FTM0_CH4/LPSPI0_SOUT/MII_RMII_MDIO/TRGMUX_IN1/QSPI_B_IO0passiveSMDoval2×0.28
PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/MII_TX_ER/QSPI_A_CS/QSPI_B_IO3/ADC0_SE11/CMP0_IN4passiveSMDoval2×0.28
PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/MII_RMII_TXD[0]/TRACE_CLKOUT/QSPI_A_IO3/ADC0_SE10/CMP0_IN5passiveSMDoval2×0.28
PTD7/LPUART2_TX/FTM2_FLT3/MII_RMII_TXD[1]/TRACE_D0/QSPI_A_IO1/CMP0_IN6passiveSMDoval2×0.28
PTD6/LPUART2_RX/FTM2_FLT2/MII_TXD2/QSPI_B_IO1/CMP0_IN7passiveSMDoval2×0.28
PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/MII_TXD3/TRGMUX_IN7/QSPI_B_IO2passiveSMDoval2×0.28
PTD12/FTM2_CH2/LPI2C1_HREQ/TRACE_D1/MII_RMII_TX_EN/LPUART2_RTS/QSPI_A_IO2passiveSMDoval2×0.28
PTD11/FTM2_CH1/FTM2_QD_PHA/TRACE_D2/MII_RMII_TX_CLK/LPUART2_CTS/QSPI_A_IO0passiveSMDoval2×0.28
PTD10/FTM2_CH0/FTM2_QD_PHB/TRACE_D3/MII_RX_CLK/CLKOUT/QSPI_A_SCKpassiveSMDoval2×0.28
VSS4passiveSMDoval2×0.28
VDD3passiveSMDoval2×0.28
PTC1/FTM0_CH1/LPSPI2_SOUT/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH7/QSPI_B_SCK/ADC0_SE9passiveSMDoval2×0.28
PTC0/FTM0_CH0/LPSPI2_SIN/MII_RMII_RXD[1]/MII_RMII_RXD[0]/FTM1_CH6/QSPI_B_RWDS/ADC0_SE8passiveSMDoval2×0.28
PTD9/LPI2C1_SCL/FXIO_D0/FTM2_FLT3/MII_RXD2/FTM1_CH5/QSPI_B_IO4passiveSMDoval2×0.28
PTD8/LPI2C1_SDA/MII_RXD3/FTM2_FLT2/FXIO_D1/FTM1_CH4/QSPI_B_IO5passiveSMDoval2×0.28
PTC17/FTM1_FLT3/CAN2_TX/LPI2C1_SCLS/MII_RMII_RX_DV/QSPI_B_IO6/ADC0_SE15passiveSMDoval2×0.28
PTC16/FTM1_FLT2/CAN2_RX/LPI2C1_SDAS/MII_RMII_RX_ER/QSPI_B_IO7/ADC0_SE14passiveSMDoval2×0.28
PTB22/FTM6_CH2/MII_CRS/LPUART1_TX/ADC0_SE19passiveSMDoval2×0.28
PTC15/FTM1_CH3/LPSPI2_SCK/MII_CRS/TRGMUX_IN8/QSPI_B_CS/ADC0_SE13passiveSMDoval2×0.28
PTB23/FTM6_CH3/LPUART1_RX/MII_COL/ADC0_SE20passiveSMDoval2×0.28
PTC14/FTM1_CH2/LPSPI2_PCS0/MII_COL/TRGMUX_IN9/ADC0_SE12passiveSMDoval2×0.28
PTB25/FTM6_CH5/LPSPI2_PCS0/ADC0_SE21passiveSMDoval2×0.28
PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7passiveSMDoval2×0.28
PTB27/FTM6_CH7/LPSPI2_SOUT/ADC0_SE22passiveSMDoval2×0.28
PTB28/FTM7_CH0/LPSPI2_SIN/ADC0_SE23passiveSMDoval2×0.28
VSS5passiveSMDoval2×0.28
VDD4passiveSMDoval2×0.28
PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6passiveSMDoval2×0.28
PTB29/FTM7_CH1/LPSPI2_SCK/ADC0_SE24passiveSMDoval2×0.28
PTC13/FTM3_CH7/FTM2_CH7/LPUART2_RTSpassiveSMDoval2×0.28
PTC12/FTM3_CH6/FTM2_CH6/LPUART2_CTSpassiveSMDoval2×0.28
PTC19/FTM7_CH5/LPSPI2_PCS1/ADC0_SE25passiveSMDoval2×0.28
PTC23/LPSPI0_SCK/ADC0_SE26passiveSMDoval0.28×2
PTC11/FTM3_CH5/FTM4_CH2/TRGMUX_IN10passiveSMDoval0.28×2
PTC10/FTM3_CH4/TRGMUX_IN11passiveSMDoval0.28×2
PTC27/FTM4_CH4/ADC0_SE27passiveSMDoval0.28×2
PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/FTM4_CH5/ADC0_SE5/ADC1_SE15passiveSMDoval0.28×2
PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/FTM4_CH6/ADC0_SE4/ADC1_SE14passiveSMDoval0.28×2
PTC28/FTM4_CH7/ADC0_SE28passiveSMDoval0.28×2
PTC9/LPUART1_TX/FTM1_FLT1/FTM5_CH0/LPUART0_RTSpassiveSMDoval0.28×2
PTC8/LPUART1_RX/FTM1_FLT0/FTM5_CH1/LPUART0_CTSpassiveSMDoval0.28×2
PTC29/FTM5_CH2/ADC0_SE29passiveSMDoval0.28×2
PTA7/FTM0_FLT2/FTM5_CH3/RTC_CLKIN/LPUART1_RTS/ADC0_SE3passiveSMDoval0.28×2
PTC30/FTM5_CH4/FXIO_D0/LPI2C1_SDAS/ADC0_SE30passiveSMDoval0.28×2
PTA6/FTM0_FLT1/LPSPI1_PCS1/FTM5_CH5/LPUART1_CTS/ADC0_SE2passiveSMDoval0.28×2
PTC31/FTM5_CH6/FXIO_D1/LPI2C1_SDA/ADC0_SE31passiveSMDoval0.28×2
PTE7/FTM0_CH7/FTM3_FLT0passiveSMDoval0.28×2
PTD18/FTM5_CH7/FXIO_D2/LPI2C1_SCLS/ADC1_SE16passiveSMDoval0.28×2
PTD19/FTM6_CH0/FXIO_D3/LPI2C1_SCL/ADC1_SE17passiveSMDoval0.28×2
VSS6passiveSMDoval0.28×2
VDD5passiveSMDoval0.28×2
PTA17/FTM0_CH6/FTM3_FLT0/*EWM_OUT/FTM5_FLT0passiveSMDoval0.28×2
PTB17/FTM0_CH5/LPSPI1_PCS3/FTM5_FLT1passiveSMDoval0.28×2
PTB16/FTM0_CH4/LPSPI1_SOUT/ADC1_SE15passiveSMDoval0.28×2
PTB15/FTM0_CH3/LPSPI1_SIN/ADC1_SE14passiveSMDoval0.28×2
PTB14/FTM0_CH2/LPSPI1_SCK/ADC1_SE9/ADC0_SE9passiveSMDoval0.28×2
PTB13/FTM0_CH1/FTM3_FLT1/CAN2_TX/FTM6_FLT0/ADC1_SE8/ADC0_SE8passiveSMDoval0.28×2
PTB12/FTM0_CH0/FTM3_FLT2/CAN2_RX/FTM6_FLT1/ADC1_SE7passiveSMDoval0.28×2
PTD22/FTM6_CH3/ADC1_SE18passiveSMDoval0.28×2
PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6passiveSMDoval0.28×2
PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/*NMI/ADC1_SE3passiveSMDoval0.28×2
PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2passiveSMDoval0.28×2
PTD23/FTM6_CH4/ADC1_SE19passiveSMDoval0.28×2
PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1passiveSMDoval0.28×2
PTA2/FTM3_CH0/LPI2C0_SDA/*EWM_OUT/FXIO_D4/LPUART0_RX/ADC1_SE0passiveSMDoval0.28×2
PTD24/FTM6_CH5/ADC1_SE20passiveSMDoval0.28×2
PTB11/FTM3_CH3/LPI2C0_HREQpassiveSMDoval0.28×2
PTB10/FTM3_CH2/LPI2C0_SDAS/SAI1_MCLKpassiveSMDoval0.28×2
PTB9/FTM3_CH1/LPI2C0_SCLS/SAI1_D0passiveSMDoval2×0.28
PTD27/FTM7_CH0/ADC1_SE21passiveSMDoval2×0.28
PTB8/FTM3_CH0/SAI1_BCLKpassiveSMDoval2×0.28
PTD28/FTM7_CH1/ADC1_SE22passiveSMDoval2×0.28
PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1passiveSMDoval2×0.28
PTD29/FTM7_CH2/ADC1_SE23passiveSMDoval2×0.28
PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0passiveSMDoval2×0.28
PTD30/FTM7_CH3/FTM6_FLT1/ADC1_SE24passiveSMDoval2×0.28
PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5passiveSMDoval2×0.28
PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4passiveSMDoval2×0.28
PTA16/FTM1_CH3/LPSPI1_PCS2/ADC1_SE13passiveSMDoval2×0.28
PTA15/FTM1_CH2/LPSPI0_PCS3/LPSPI2_PCS3/FTM7_FLT0/ADC1_SE12passiveSMDoval2×0.28
PTE6/LPSPI0_PCS2/FTM7_FLT1/FTM3_CH7/LPUART1_RTS/ADC1_SE11passiveSMDoval2×0.28
PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/SAI1_SYNC/ADC1_SE10passiveSMDoval2×0.28
VSS7passiveSMDoval2×0.28
VDD6passiveSMDoval2×0.28
PTE19/FTM7_CH7/ADC1_SE25passiveSMDoval2×0.28
PTE20/FTM4_CH0/ADC1_SE26passiveSMDoval2×0.28
PTA14/FTM0_FLT0/FTM3_FLT1/EWM_IN/FTM1_FLT0/SAI0_D3passiveSMDoval2×0.28
PTE21/FTM4_CH1/ADC1_SE27passiveSMDoval2×0.28
PTE22/FTM4_CH2/ADC1_SE28passiveSMDoval2×0.28
PTA13/FTM1_CH7/CAN1_TX/LPI2C1_SCLS/FTM2_QD_PHA/SAI0_D0passiveSMDoval2×0.28
PTE23/FTM4_CH3/ADC1_SE29passiveSMDoval2×0.28
PTE24/FTM4_CH4/CAN2_TX/ADC1_SE30passiveSMDoval2×0.28
PTE25/FTM4_CH5/CAN2_RX/ADC1_SE31passiveSMDoval2×0.28
PTA12/FTM1_CH6/CAN1_RX/LPI2C1_SDAS/FTM2_QD_PHB/SAI0_BCLKpassiveSMDoval2×0.28
PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT/SAI0_SYNCpassiveSMDoval2×0.28
PTA10/FTM1_CH4/FXIO_D0/JTAG_TDOpassiveSMDoval2×0.28
PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPI2C1_SCL/LPSPI1_PCS0/FTM1_FLT1/SAI0_D1passiveSMDoval2×0.28
PTE0/LPSPI0_SCK/TCLK1/LPI2C1_SDA/LPSPI1_SOUT/FTM1_FLT2/SAI0_D2passiveSMDoval2×0.28
PTC5/FTM2_CH0/RTC_CLKOUT/LPI2C1_HREQ/FTM2_QD_PHB/JTAG_TDIpassiveSMDoval2×0.28
PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2passiveSMDoval2×0.28
PTA5/TCLK1/*RESETpassiveSMDoval2×0.28
PTA4/CMP0_OUT/*EWM_OUT/JTAG_TMS/SWD_DIOpassiveSMDoval2×0.28
PTA9/LPUART2_TX/LPSPI2_PCS0/FXIO_D7/FTM3_FLT2/FTM1_FLT3/FTM4_FLT0passiveSMDoval2×0.28
PTA8/LPUART2_RX/LPSPI2_SOUT/FXIO_D6/FTM3_FLT3/FTM4_FLT1passiveSMDoval2×0.28

Key Parameters

Frequency
80MHz

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Details

Category
microcontroller
MPN
FS32K148HAT0VLQT
Manufacturer
NXP Semicon
Package
LQFP-144(20x20)
Footprint
LQFP-144_L20.0-W20.0-P0.50-LS22.0-BL
JLCPCB
C1345090
LCSC
C1345090
Lifecycle
active
Mounting
SMT
RoHS
Compliant
MSL
MSL 3
ECCN
5A992C

JLCPCB Stock & Pricing

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